| Course title | |||||
| 並列処理特論 [Parallel Processing] | |||||
| Course category | courses for doctoral programs | Requirement | Credit | 2 | |
| Department | Year | ～ | Semester | Fall | |
| Course type | Fall | Course code | 1080443 | ||
| Instructor(s) | |||||
| 中條 拓伯 [NAKAJO Hironori] | |||||
| Facility affiliation | Faculty of Engineering | Office | Email address | ||
| Course description |
|
Currently, high performance computers consist of multiple computers connected via network and perform parallel processing efficiently. In this class, we discuss processor technologies especially on cache memory in a computing system. Cache technology for multi-processing is discussed, too. |
| Expected Learning |
| Advanced knowledge on inner processor architecture and system architecture for the future advanced computing system. |
| Course schedule |
|
Lectures in the class are given as follows. 1. What is computer architecture? 2. Bottleneck of Von Neumann architecture 3. Numerical description in a computer system 1: integer and fixed point numbers 4. Numerical description in a computer system 2: floating point numbers 5. Virtual memory technology 6. How to implement virtual memory with hardware 7. Cache memory technology 8. How to implement cache memory with hardware 9. Multi-level cache system for a high-end processor 10. New cache memory system for a multi-core processor architecture |
| Prerequisites |
| Required Text(s) and Materials |
| PPT file given in every lecture |
| References |
| John L. Hennessy and David Patterson: "Computer Architecture Quantitative Approach 5th Edition" |
| Assessment/Grading |
|
Small report in each lecture Final report on dedicated topics in advanced computing system |
| Message from instructor(s) |
| Course keywords |
| Office hours |
| Remarks 1 |
| Remarks 2 |
| Related URL |
| Lecture Language |
| English |
| Language Subject |
| English |
| Last update |
| 3/22/2018 1:50:51 PM |