| Course title | |||||
| 論理回路 [Logic Circuit] | |||||
| Course category | technology speciality courses | Requirement | Credit | 2 | |
| Department | Year | 1～4 | Semester | 3rd | |
| Course type | 3rd | Course code | 021619 | ||
| Instructor(s) | |||||
| 近藤 敏之 [KONDO Toshiyuki] | |||||
| Facility affiliation | Faculty of Engineering | Office | afjgxte/L1151 | Email address | |
| Course description |
|
Class code: ffx7tpl a. Purpose To learn the design method of logic circuits with binary logic gates and to analyze the function and operation speed of given logic circuits using these logic gates. In addition, it will be possible to design logic circuits such as simple computing units, counters, control circuits and so on. b. Overview 1. Basic logic operation and Boolean algebra. Binary number. 2. Combinatorial circuit: arithmetic unit, selection circuit, etc. 3. Sequential circuit: counter, control circuit, etc. |
| Expected Learning |
|
・ Understand representation of numerical values by binary numbers, and can master Boolean algebra ・ Understand expressing methods and mechanisms of combinational logic circuits, and can analyze and design ・ Understand the operation of sequential logic circuit, can analyze and design See the Curriculum maps. |
| Course schedule |
|
After every lecture, we will conduct an exercise, we will deepen our understanding of what we learned on that day and adjust the progress without confirming the degree of comprehension. #1. Logic circuit, N-ary number, representation of negative number, binary number, #hexadecimal number #2. Analysis of logic function, MIL symbol, truth table, Boolean algebra, logic circuit diagram #3. Product-sum / sum product standard type, expansion method to standard form, exclusive OR #4. Simplification of logic functions using complete system, Carnot diagram #5 Simplification of incomplete definition logic function, Quine ・ McCluskey method #6 Analysis and synthesis of combinational logic circuits, circuit delay and timing chart #7 An adder, a subtracter, an adder-subtractor, a parity #8 Summary of a combinational logic circuit mid-term exam #9-10 Sequential circuit, state transition, flip-flop, edge trigger and master-slave Synthesis method of synchronous sequential circuit #12 Synchronous sequential circuit analysis method, sequential circuit timing design and operation speed #13-14 Sequential function block, asynchronous counter design # Summary of Sequential circuit Final exam |
| Prerequisites |
| In addition to 30 hours that students spend in the class, students are recommended to prepare for and revise the lectures, spending the standard amount of time as specified by the University. |
| Required Text(s) and Materials |
| none |
| References |
|
- Kunio Murakami, Tsutomu Ishikawa "Introduction to logic circuits for computer understanding", Kyoritsu Publishing. - Naofumi Takagi "Logic Circuit", Ohm-sha - D.Harris et al. "Digital design and computer architecture", Shoeisha |
| Assessment/Grading |
|
Your grade point is determined based on both mid-term and final exams. The GPA distribution is adjusted to balance with the other class. |
| Message from instructor(s) |
| You can understand the basics of the processing performed by the computer that plays the core of IT. |
| Course keywords |
| Binary number, Boolean algebra, Combinatorial circuit, Sequential circuit, State transition |
| Office hours |
| Ask questions at any time by email. |
| Remarks 1 |
| Remarks 2 |
| Related URL |
| Lecture Language |
| Japanese |
| Language Subject |
| Last update |
| 9/16/2021 10:12:42 AM |