| Course title | |||||
| 論理回路 [Logic Circuit] | |||||
| Course category | technology speciality courses | Requirement | Credit | 2 | |
| Department | Year | 1～4 | Semester | 3rd | |
| Course type | 3rd | Course code | 021620 | ||
| Instructor(s) | |||||
| 藤吉 邦洋 [FUJIYOSHI Kunihiro] | |||||
| Facility affiliation | Faculty of Engineering | Office | Email address | ||
| Course description |
|
a. Purpose To learn the design method of logic circuits with binary logic gates and to analyze the function and operation speed of given logic circuits using these logic gates. In addition, it will be possible to design logic circuits such as simple computing units, counters, control circuits and so on. b. Overview 1. Basic logic operation and Boolean algebra. Binary number. 2. Combinatorial circuit: arithmetic unit, selection circuit, etc. 3. Sequential circuit: counter, control circuit, etc. 4. Circuit Delay and Timing Chart, Timing Constraint |
| Expected Learning |
|
・ Understand representation of numerical values by binary numbers, and can master Boolean algebra ・ Understand expressing methods and mechanisms of combinational logic circuits, and can analyze and design ・ Understand the operation of sequential logic circuit, can analyze and design See the Curriculum maps. |
| Course schedule |
|
After every lecture, we will conduct an exercise, we will deepen our understanding of what we learned on that day and adjust the progress without confirming the degree of comprehension. 1-7) ・ Logic circuit is a hierarchical design of LSI, N-ary number, representation of negative number, binary number, hexadecimal number ・ Analysis of logic function, MIL symbol, truth table, Boolean algebra, logic circuit diagram ・ Product-sum / sum product standard type, expansion method to standard form, exclusive OR ・ Simplification of logic functions using complete system, Carnot diagram ・ Simplification of incomplete definition logic function, Quine ・ McCluskey method ・ Analysis and synthesis of combinational logic circuits, circuit delay and timing chart An adder, a subtracter, an adder-subtractor, a parity 8) Combination circuit summary Exam. 9-14) ・ Sequential circuit, state transition, flip-flop, edge trigger and master-slave Synthesis method of synchronous sequential circuit ・ Synchronous sequential circuit analysis method, sequential circuit timing design and operation speed ・ Sequential function block, asynchronous counter design 15) Sequential circuit summary Exam. |
| Prerequisites |
| Students are expected to have the standard 「Break time just after the lectureamount of time to prepare for and review the lecture as specified by the University. |
| Required Text(s) and Materials |
| none |
| References |
|
Important reference book: Kunio Murakami, Tsutomu Ishikawa "Introduction to logic circuits for computer understanding", Kyoritsu Publishing. Reference book: Naofumi Takagi "Logic Circuit", Shokodo. |
| Assessment/Grading |
|
Intermediate test (45 to 50%), final exam (45 to 50%), exercise point (0 to 10%), Or average point only for mid-term exam and final examination, Evaluate by the better one. |
| Message from instructor(s) |
| You can understand the basics of the processing performed by the computer that plays the core of IT. |
| Course keywords |
| Binary number, Boolean algebra, Combinatorial circuit, Sequential circuit, State transition |
| Office hours |
| Break time just after the lecture |
| Remarks 1 |
| Remarks 2 |
| Related URL |
| Lecture Language |
| Japanese |
| Language Subject |
| Last update |
| 3/14/2022 1:55:02 PM |